1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and particularly to a method of fabricating a vertical MOSFET including a trench gate.
2. Description of Related Art
In recent years, high integration of a semiconductor device is rapidly proceeding by development of microfabrication technology. Above all, a vertical MOSFET including a gate electrode deposited in a trench is widely known as a semiconductor device that realizes low on-resistance and high withstand voltage. Such vertical MOSFET is formed by forming a trench in an epitaxial layer, and depositing a gate electrode made of polysilicon or the like in the trench.
Then, in the vertical MOSFET, an on-resistance (hereinafter also referred to as Ron) is greatly dependent on the resistance of an epitaxial layer, and the resistance of the epitaxial layer decreases as the dope concentration to the epitaxial layer increases. On the other hand, the withstand voltage between a drain and a source decreases as the dope concentration to the epitaxial layer increases. Therefore, there is a trade-off between the on-resistance and the withstand voltage between a drain and a source of the vertical MOSFET. Accordingly, there is an optimal dope concentration of the epitaxial layer in light of the on-resistance and the withstand voltage between a drain and a source, and the dope concentration cannot be increased more than a certain concentration.
FIG. 6 is a cross-sectional diagram of the vertical MOSFET disclosed in P. Moens “Record-low on-Resistance for 0.35 μm based integrated XtreMOS™ Transistors” Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs May 27-30, 2007, Jeju, Korea. The vertical MOSFET illustrated in FIG. 6 includes a trench 102 formed in an n type epitaxial layer 101. A field oxide film 104 is formed in the trench 102, and an n type gate polysilicon electrode 106 is formed to be surrounded by the field oxide film 104. Further, a pad oxide film 103 and a gate oxide film 105 are formed near the surface of the trench 102. Then, a p type body layer region 107 and an n type source region 108 are formed between each trench 102.
In order to fabricate the vertical MOSFET illustrated in FIG. 6, the n type epitaxial layer 101 is formed first. Then, a first trench having trench depth of about 1.5 μm is formed in the n type epitaxial layer 101 by etching, so as to form the pad oxide film 103 and a nitride film. Then, a second trench having trench depth of about 6.5 μm is formed in the n type epitaxial layer 101. This trench depth is to be the depth of the trench 102 illustrated in FIG. 6. After forming the second trench, the section where no nitride film is formed is oxidized by thermal oxidization, and then the field oxide film 104 of about 600 nm is formed. After that, the nitride film is removed, and the gate oxide film 105 of about 50 nm is formed by thermal oxidation. Then, the n type gate polysilicon electrode 106 is formed by depositing polysilicon in the trench 102. Further, the p type body region 107 and the n type source region 108 are formed, so as to fabricate the vertical MOSFET illustrated in FIG. 6.
As illustrated in FIG. 6, by forming the field oxide film 104 having a thicker film than the gate oxide film to a part of the vertical MOSFET trench 102, the withstand voltage between a drain and a source can be improved. Then, the concentration of an impurity to dope into the n type epitaxial layer 101 can be increased, thereby enabling to reduce the on-resistance Ron of the vertical MOSFET.